[Computer Architecture] MIPS, ARM, RISC-V, System verilog

Review)

RISC는 시험에 나오지 않음 (MIPS와 유사하기 때문에)

ARM v8 instruction (from COD)

• In moving to 64-bit, ARM did a complete overhaul.
• ARM v8 resembles MIPS
• Changes from v7:
  • No conditional execution field
  • Immediate field
  • Dropped load/store multiple
  • PC is no longer a GPR
  • GPR set expanded to 32
  • Addressing modes work for all word sizes
  • Divide instruction
  • Branch if equal/branch if not equal instruction

MIPS와 거의 유사함

Intel x86 Register

flag register

register 수가 MIPS에 비해서 현저히 적다.

Intel x86 Instructions

RISC에서는 fetch할 때 32bit만 가져오면 됐는데 CISC는 위와 같이 32bit로 고정되어 있지 않다.

그래서 CISC는 고정된 bit를 fetch하는 것이 아니라. instruction buffer라는 곳에 몽땅 다 넣어서 명령어가 몇 bit인지 decode한 후에 명령어를 가져온다(fetch).

MIPS and RISC-V

MIPS와 비교했을 때, RISC-V는 opcode가 뒤쪽으로 가 있다.

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RISC-V Register Set

Branching

• Execute instructions out of sequence
• Types of brances:
  • Conditional
    • branch if equal (beq)
    • branch if not equal (bne)
    • branch if less than (blt)
    • branch if greater than or equal (bge)
  • Unconditional
    • jump(j)
    • jump register(jr)
    • jump and link(jal)
    • jump and link register(jalr)

RISC-V Function Calling Conventions

• Call Function: jump and link (jal func)
• Return from function: jump register (jr ra)
• Arguments: a0 – a7
• Return value: a0

Preserved Registers

Machine Language

• Binary representation of instructions
• Computers only understand 1’s and 0’s
• 32-bit instructions
• Simplicity favors regularity: 32-bit data & instructions
• 4 Types of Instruction Formats:
• R-Type
• I-Type
• S/B-Type
• U/J-Typ

U/J-Type

• Upper - immediate-Type
• Jump-Type
• Differ only in immediate encoding

Review: Instruction Formats

MIPS의 R,I, J와 거의 유사하다.

Compressed instructions

• 16-bit RISC-V instructions
  • register 32-bit을 다 쓰지 않아 더 가볍지만 할 수 있는 명령이 제한되기 때문에 microprocessor나 embedded에 사용된다.
• Replace common integer and floating-point instructions with 16-bit versions.
• Most RISC-V compilers/processors can use a mix of 32-bit and 16-bit instructions (and use 16-bit instructions whenever possible).
• Uses prefix: c.

Compressed Machine Formats

RISC-V Floating-Point Extensions

• RISC-V offers three floating point extensions:
• RVF: single-precision (32-bit)
• 8 exponent bits, 23 fraction bits
• RVD: double-precision (64-bit)
• 11 exponent bits, 52 fraction bits
• RVQ: quad-precision (128-bit)
• 15 exponent bits, 112 fraction bits

Exceptions

MIPS와 마찬가지임 전 강의 참조.

RISC-V Instructions

MIPS와 거의 같다.