[Computer Architecture] System Veriolog

Chapter 4

Computer systems Abstraction

• HDL을 할 때는 RTL level에서 함

• RTL level: register에 담아놨다가 사용

• HDL -> gate level : synthesis

synthesizable한 것에 대해서 simulation.

전체 feature는 simulation을 위한 것.

우리가 관심을 가질 내용은 synthesis보다는 processor를 설계하는 것.(modeling simulation)

HDL to Gates

• Simulation
  • Inputs applied to circuit
  • Outputs checked for correctness
  • Millions of dollars saved by debugging in simulation instead of hardware
• Synthesis
  • Transforms HDL code

Blocking vs. Nonblocking Assignment

• <= is nonblocking assignment
  • Occurs simultaneously with others
• = is blocking assignment
  • Occurs in order it appears in file

Testbenches

• HDL that tests another module: device under test (dut)